1. Field of the Invention
The present invention relates to semiconductor integrated circuit architecture for reducing undesirable off-leak currents through MOS transistors.
2. Description of the Related Art
One issue in the advance of the high-density integration of semiconductor devices is the increase in the off-leak current, which designates the current undesirably flowing through off-state MOS transistors. In recent semiconductor devices, the off-leak current accounts for large percentages of total power consumption. Therefore, various techniques have been proposed for reducing the power consumption resulting from the off-leak current.
One approach for reducing the off-leak current is the MT-CMOS (multi-threshold CMOS) technology. Japanese Laid-Open Patent Application No. JP-A 2004-186666 discloses a semiconductor device based on the MT-CMOS technology. FIG. 1 illustrates the structure of the disclosed semiconductor device, which is denoted by the numeral 100. The semiconductor device 100 includes a virtual power supply line Vddv in addition to a power supply line Vdd. The virtual power supply line Vddv is connected to the power supply line Vdd through an NMOS transistor Q1 having a relatively high threshold voltage, which is often called “sleep transistor”. The virtual power supply line Vddv is used to feed the power supply voltage to load circuits 101, which are composed of NMOS transistors having a relatively low threshold voltage (denoted by the numerals Q4 and Q5), and PMOS transistors having a relatively low threshold voltage (denoted by the numerals Q2 and Q3). The load circuits 101 are located in specific regions (such, as function blocks), and the power supply to the respective load circuits 101 is implemented in units of the specific regions. In the conventional semiconductor device 100 shown in FIG. 1, the off-leak currents through the load circuits 100 are reduced by the control of a signal PNCT inputted to the gate of the high-threshold NMOS transistor Q1.
FIGS. 2A to 2C illustrate variations of the configuration of the conventional semiconductor circuit based on the MT-CMOS technology. FIG. 2A illustrates an exemplary arrangement of function cells 102 within the load circuits 101. The structure of each load circuit 101 is determined on the combination of the function cells 102. In one MT-CMOS semiconductor circuit, as shown in FIG. 2B, a high-threshold PMOS transistor Q1-1 is used as a sleep transistor to feed the power supply voltage to a load circuit 101-1 composed of three function cells 102, while another high-threshold PMOS transistor Q1-2 is used as another sleep transistor to feed the power supply voltage to a load circuit 101-2 composed of a single function cell 102. In another MT-CMOS semiconductor circuit, as shown in FIG. 2C, a high-threshold PMOS transistor Q1-3 is used to feed the power supply voltage to a load circuit 101-3, while another high-threshold PMOS transistor Q1-4 is used to feed the power supply voltage to a load circuit 101-4. Both of the load circuits 101-3 and 101-4 are composed of two function cells 102.
One issue of the MT-CMOS technology is proper transistor sizing of sleep transistors, such as the high-threshold NMOS transistor Q1 and PMOS transistors Q1-1 to Q1-4. The load circuits 101 may differ in the circuit scale, and therefore currents to be fed to the respective load circuits 101 are dependent on the circuit scales thereof. However, proper transistor sizing of the sleep transistors requires a complicated circuit design process.
U.S. Unexamined Patent Application Publication No. 2005/0200383A1 and the corresponding Japanese Patent Laid Open Patent Application No. 2005-259879 discloses a technique in which power switch cells are distributedly arranged over a circuit cell area. The power supply through the power switch cells is finely controlled for each set of a relatively reduced number of circuit cells. This effectively reduces the voltage drop across the power switches, and improves flexibility of the arrangement of the power switch cells.